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| deflection processor for multisync monitors s1d2511b01 1 deflection processor the s1d2511b01 is a monolithc integrated circuit assembled in 32 pins shrunk dual in line plastic pack- age. this ic controls all the functions related to the hori- zontal and vertical deflection in multimodes or multi- frequency computer display monitors. the internal sync processor, combined with the very powerful geometry correction block make the s1d2511b suitable for very high performance monitors with very few external components. the horizontal jitter level is very low. it is particularly well suited for high-end 15 ? and 17 ? monitors. functions ? defiection processor ? i 2 c bus control ? b+ regulator ? vertical parabola generator ? horizontal and vertical dynamic focus features (horizontal) ? self-adaptative ? dual pll concept ? 150khz maximum frequency ? x-ray protection input ? i 2 c controls : horizontal duty-cycle, h-position,free running frequency, frequency generator for burn-in mode. (vertical) ? vertical ramp generator ? 50 to 165hz agc loop ? geometry tracking with v-pos & amp ? i 2 c controls : v-amp, v-pos, s-corr, c-corr (i 2 c geometry corrections) ? vertical parabola generator (pincushion-e/w, keystone) ? horizontal dynamic phase (side pin balance & parallelogram) ? horizontal and vertical dynamic focus (horizontal focus amplitude, horizontal focus symmetry, vertical focus amplitude) (general) ? sync processor ? 12v supply voltage ? hor. & vert, lock/unlock outputs ? read/write i 2 c interface ? vertical moire ? b+ regulator -internal pwm generator for b+ current mode step-up converter. - switchable to step-down converter - i 2 c adjustable b+ reference voltage - output pulses synchronized on horizontal frequency - internal maximum current limitation. ordering information device package operating temperature S1D2511B01-A0b0 32-sdip 0 c ? 70 c 32-sdip-400
s1d2511b01 deflection processor for multisync monitors 2 block diagram 19 16 15 28 14 9 phase/ frequency comparator h-phase(7 bits) lock/unlock identification phase comparator vco safety processor phase shifter h-duty (5 bits) 7 3 8 5 6 12 4 b+ controller 10 i c interface geometry tracking 22 20 23 vaccap comp pll1f hlockout r0 c0 hfly pll2c hout vout v ref forced freq. 2 bits free running 5 bits hout buffer 26 13 sync input select (1bit) sync processor v ref 21 1 2 25 29 27 30 31 32 vcc xray reset generator 2 x 2 x 2 moire cancel 5 bits+on/off + + + 17 + 24 b+ adjust 7 bits vsync s and c correction vertical oscillator ramp generator 6 bits 8 bits vpos 7bits keyst 6 bits pcc 7 bits vamp 6 bits x 2 x x 2 amp & symmetry 2x5 bits spin bal 6 bits key bal 6 bits vamp 7 bits h position b+ out regin bgnd hfocus cap focus i sense ewout vcap h/hvin href vsync in vcc xray vref vgnd 5v sda scl gnd 11 hgnd 18 breath deflection processor for multisync monitors s1d2511b01 3 pin configurations vref sda scl c0 r0 hposition pll1f pll2c xray hout vgnd ewout vcc gnd 9 3 2 1 6 5 8 7 27 21 31 30 25 26 10 19 29 24 vagccap comp hfly 4 14 12 28 hfocuscap hlockout vsyncin h/hvin 13 focusout href 11 hgnd 20 bout 5v vout 32 22 vcap 23 s1d2511b 15 16 18 17 regin isense breath b+gnd s1d2511b01 deflection processor for multisync monitors 4 pin description table 1. pin description no pin name description 1 h/hvin ttl compatible horizontal sync input(separate or composite) 2 vsyncin ttl compatible vertical sync input (for separated h&v) 3 hlockout first pll lock/unlock output (0v unlocked - 5v locked) 4 pll2c second pll loop filter 5 c0 horizontal oscillator capacitor 6 r0 horizontal oscillator resistor 7 pll1f first pll loop filter 8 hposition horizontal position filter(capacitor to be connected to hgnd) 9 hfocuscap horizontal dynamic focus oscillator capacitor 10 focusout mixed horizontal and vertical dynamic focus output 11 hgnd horizontal section ground 12 hfly horizontal flyback input (positive polarity) 13 href horizontal section reference voltage (to be filtered) 14 comp b+ error amplifier output for frequency compensation and gain setting 15 regin regulation input of b+ control loop 16 isense sensing of external b+ switching transistor current or switch for step-down converter 17 b+gnd ground (related to b+ reference adjustment) 18 breath dc breathing input control(compensation of vertical amplitude against ehv variation) 19 vgnd vertical section ground 20 vagccap memory capacitor for automatic gain control loop in vertical ramp generator 21 vref vertical section reference voltage (to be filtered) 22 vcap vertical sawtooth generator capacitor 23 vout vertical ramp output (with frequency independant amplitude and s or c corrections if any). it is mixed with vertical position voltage and vertical moire. 24 ewout pincushion-east/west correction parabola output 25 xray x-ray protection input (with internal latch function) 26 hout horizontal drive output (internal transistor, open collector) 27 gnd general ground (referenced to vcc) 28 bout b+ pwm regulator output 29 vcc supply voltage (12v typ) 30 scl i 2 c clock input 31 sda i 2 c data input 32 5v supply voltage (5v typ) deflection processor for multisync monitors s1d2511b01 5 reference data table 2. reference data parameter value unit horizontal frequency 15 to 150 khz autosynch frequency (for given r0 and c0) 1 to 4.5fo fh horizontal sync polarity input yes polarity detection (on both horizontal and vertical section) yes ttl composite synch yes lock/unlock identification (on both horizontal 1st pll and vertical section) yes i 2 c control for h-position 10 % xray protection yes i 2 c horizontal duty cycle adjust 30 to 60 % i 2 c free running frequency adjustment 0.8 to 1.3fo fh stand-by function yes dual polarity h-drive outputs no supply voltage monitoring yes pll1 inhibition possibility no blanking output no vertical frequency 35 to 200 hz vertical autosync (for 150nf on pin22 and 470nf on pin20) 50 to 165 hz vertical s-correction yes vertical c-correction yes vertical amplitude adjustment yes dc breathing control on vertical amplitude yes east/west parabola output(also known as pin cushion output) yes east/west correction amplitude adjustment yes keystone adjustment yes internal dynamic horizontal phase control yes side pin balance amplitude adjustment yes parallelogram adjustment yes tracking of geometric corrections with vertical amplitude and position yes s1d2511b01 deflection processor for multisync monitors 6 reference voltage (both on horizontal and vertical) yes dynamic focus (both on horizontal and vertical) yes i 2 c horizontal dynamic focus amplitude adjustment yes i 2 c horizontal dynamic focus symmetry adjustment yes i 2 c vertical dynamic focus amplitude adjustment yes deflection of input sync type(biased from 5v alone) yes vertical moire output yes i 2 c controlled v-moire amplitude yes frequency generator for burn-in yes fast i 2 c read/write 400 khz b+ regulation adjustable by i 2 c yes table 2. reference data (continued) parameter value unit deflection processor for multisync monitors s1d2511b01 7 absolute maximum ratings thermal characteristics sync processor operating codnitions no item symbol value unit 1 supply voltage (pin 29) v cc 13.5 v 2 supply voltage (pin 32) v dd 5.7 v 3 maximum voltage on pin 4 pin 9 pin 5 pins 6,7,8,14,15,16,20,22 pins 10,18,23,24,25,26,28 pins 1,2,3,30,31 v in 4.0 5.5 6.4 8.0 v cc v dd v v v 4 esd susceptibillty human body model, 100pf discharge through 1.5k w eiaj norm, 200pf discharge through 0 w vesd 2 300 kv v 5 storage temperature tstg - 40, +150 c 6 operating temperature topr 0, +70 c no item symbol value unit 1 junction temperature tj +150 c 2 junction-ambient thermal resistance q ja 65 c/w table 3. sync processor operating codnitions parameter symbol conditions min typ max unit horizontal sync input voltage hsvr pin 1 0 5 v minimum horizontal input pulse duration mind pin 1 0.7 m s maximum horizontal input signal duty cycle mduty pin 1 25 % vertical sync input voltage vsvr pin 2 0 5 v minimum vertical sync pulse width vsw pin 2 5 m s maximum vertical sync input duty cycle vsmd pin 2 15 % maximum vertical sync width on ttl h/v composite vextm pin 1 750 m s sink and source current i hlockout pin 3 250 m a s1d2511b01 8 electrical characteristics ( v = 5v, tamb = 25 i 2 (see also i 2 2 c sub address control) table 4. sync processor electrical characteristics symbol conditions typ max horizontal and vertical input threshold voltage (pin 1, 2) low level high level 0.8 v horizontal and vertical pull-up resister rin 200 k falling and rising output cmos buffer tfrout 200 ns (pin 3) vhlock lockout = -250 a unlocked, i = +250 m 0 5 v v th (9) voutt c0 = 820pf 35 % 2 c read/write operating conditions symbol min max unit vinh 3.0 5.0 v vinl 0 1.5 v fscl - 200 khz tbuf 1.3 - us thds 0.6 - us tsup 0.6 - us tlow 1.3 - us thigh 0.6 - us thdat 0.3 - us tsupdat 0.25 - us tr - 1.0 us tf - 3.0 us deflection processor for multisync monitors s1d2511b01 9 i 2 c bus timing requirement electrical characteristics ( v dd = 5v, tamb = 25 c) horizontal section operating conditions table 6. i 2 c read/write electrical characteristics parameter symbol conditions min typ max unit i 2 c processor maximum clock frequency fscl pin 30 400 khz low period of the scl clock tlow pin 30 1.3 m s high period of the scl clock thigh pin 30 0.6 m s sda and scl input threshold vinth pin 30, 31 2.2 v acknowledge output voltage on sda input with 3ma vack pin 31 0.4 v table 7. horizontal section operating conditions parameter symbol conditions min typ max unit vco minimum oscillator resistor r 0(min.) pin 6 6 k w minimum oscillator capacitor c 0(min.) pin 5 390 pf maximum oscillator frequency f (max.) 150 khz output section maximum input peak current i12m pin 12 5 ma horizontal drive output maximum current hoi pin26, sunk current 30 ma tbuf start:clock high stop:clock high sda scl tlow thds tsupdat data change:clock low tsup thdat thigh s1d2511b01 deflection processor for multisync monitors 10 electrical characteristics ( v dd = 5v, tamb = 25 c) table 8. horizontal section electrical characteristics parameter symbol conditions min typ max unit supply and reference voltage supply voltage vcc pin 29 10.8 12 13.2 v supply voltage v dd pin 32 4.5 5 5.5 v supply current i cc pin 29 50 ma supply current i dd pin 32 5 ma horizontal reference voltage v ref-h pin 13, i=-2ma 7.4 8 8.6 v vertical reference voltage v ref-v pin 21, i=-2ma 7.4 8 8.6 v max. sourced current on v ref-h i ref-h pin 13 5 ma max. sourced current on v ref-v i ref-v pin 21 5 ma 1st pll section polarity integration delay hpoit pin 1 0.75 ms vco control voltage (pin 7) v vco v ref-h =8v f0 fh (max.) 1.3 6.2 v v vco gain (pin 7 ) v cog r 0 =6.49k w , c 0 =820pf, df/dv=1/11r 0 c 0 17 khz/v horizontal phase adjustment (11) hph % of horizontal period 10 % horizontal phase setting value(pin 8) (11) minimum current value typical value maximum value hphmin hphtyp hphmax sub-address 01 byte x 1111111 byte x 1000000 byte x 0000000 2.6 3.2 3.8 v v v pll1 filter current charge ipii1u ipii1l pll1 is unlocked pll1 is locked 140 ? 1 m a ma free running frequency fo r 0 =6.49k w ,c 0 =820pf, f 0 =0.97/8r 0 c 0 140 1 m a ma free running frequency thermal drift (no drift on external components) (7) df0/dt -150 ppm/c free running frequency adjustment minimum value maximum value f 0 (min.) f 0 (max.) sub-address 02 byte x x x 11111 byte x x x 00000 0.8 1.3 f0 f0 pll1 capture range cr r 0 =6.49k w ,c 0 =820pf, from f 0 +0.5khz to 4.5fo fh(min.) fh(max.) 100 23.5 khz khz safe forced frequency sf1 byte 11 x x x x x x sf2 byte 10 x x x x x x sff sub-address 02 2f0 3f0 2nd pll section horizontal output section deflection processor for multisync monitors s1d2511b01 11 flyback input threshold voltage (pin12) fbth 0.65 0.75 v horizontal jitter hjit 70 ppm horizontal drive output duty-cycle (pin 26) (1, 2) low level high level hdmin hdmax sub-address 00 byte xxx11111 byte xxx00000 (2) 30 60 % % x-ray protection input threshold voltage xrayth pin 25 (12) 8 v internal clamping levels on 2nd pll loop filter (pin 4 ) vphi2 low level high level 1.6 3.7 v v threshold voltage to stop h-out, v-out when v cc < vscinh vscinh pin 29 7.5 v horizontal drive output (low level) hdvd pin 26 i out =30ma 0.4 v horizontal dynamic focus function horizontal dynamic focus sawtooth minimum level maximum level hdfst capacitor on hfocuscap and c0=820pf, th=20 m s, pin 9 2 4.7 v v horizontal dynamic focus sawtooth discharge width hdfdis start by hfly center 400 ns bottom dc output level hdfdc r load =10k w , pin 10 2 v dc output voltage thermal drift tdhdf 200 ppm/c horizontal dynamic focus amplitude min byte xxx11111 typ byte xxx10000 max byte xxx00000 hdfamp sub-address 03, pin 10, fh=50khz, keystone typ 1 1.5 3 vpp vpp vpp horizontal dynamic focus keystone min a/b byte xxx11111 typ byte xxx10000 max byte xxx00000 hdfkeyst sub-address 04, fh = 50khz, typ amp b/a a/b a/b 2.2 2.2 3.5 1.0 3.5 vertical dynamic focus function (positive parabola) vertical dynamic focus parabola (added to horizontal one) amplitude with vout and vpos typical min. byte 000000 typ. byte 100000 max. byte 111111 ampvdf sub-address 0f 0 0.5 1 vpp vpp vpp parabola amplitude function of vamp (tracking between vamp and vdf) with vpos typ. (see figure 1) (3) vdfamp sub-address 05 byte 10000000 byte 11000000 byte 11111111 0.6 1 1.5 vpp vpp vpp parabola assymetry function of vpos control (tracking between vpos and vdf) with vamp max. vhdfkeyt sub-address 06 byte x0000000 byte x1111111 0.52 0.52 vpp vpp table 8. horizontal section electrical characteristics (continued) parameter symbol conditions min typ max unit s1d2511b01 deflection processor for multisync monitors 12 vertical section operating conditions electrical characteristics (v cc = 12v, tamb = 25 c) table 9. vertical section operating conditions parameter symbol conditions min typ max unit outputs section maximum ew output voltage vewm pin 24 6.5 v minimum ew output voltage vewm pin 24 1.8 v minimum load for less than 1% vertical amplitude drift r load pin 20 65 m w table 10. vertical section electrical characteristics parameter symbol conditions min typ max unit vertical ramp section voltage at ramp bottom point vrb v ref-v =8v, pin 22 2 v voltage at ramp top point (with sync) v ref-v vrt v ref-v =8v, pin 22 5 v voltage at ramp top point (without sync) vrtf pin 22 vrt-01 v vertical sawtooth discharge time duration (pin 22) vstd with 150nf cap 70 m s vertical free running frequency see (4, 5) vfrf c osc(pin22) =150nf measured on pin 22 100 hz auto -sync frequency (13) asfr c 22 =150nf 5% see (6) 50 165 hz ramp amplitude drift versus frequency at maximum vertical amplitude rafd c 22 =150nf 50hz s1d2511b01 deflection processor for multisync monitors 14 b+ section operating conditions electrical characteristics (v cc = 12v, tamp = 25 c ) vertical moire vertical moire (measured on voutdc) pin 23 vmoire sub address 0c byte 01x11111 6 mv breathing compensation dc breathing control range (15) brrang v18 1 12 v vertical output variation versus dc breathing con- trol (pin 23) bradj v18 3 v ref-v v18=4v 0 -10 % % table 11. b+ section operating conditions parameter symbol conditions min typ max unit minimum feedback resistor feedres resistor between pins 15 and 14 5 k w table 12. b+ section electrical characteristics parameter symbol conditions min typ max unit error amplifier open loop gain olg at low frequency (10) 85 db unity gain band width ugbw see (7) 6 mhz regulation input bias current iri current sourced by pin 15 (pnp base) 0.2 m a maximum guaranted error amplifier output current eaoi current sourced by pin 14 current sunk by pin 14 0.5 2 ma ma current sense input voltage gain csg pin 16 3 max current sense input thres hold voltage mceth pin 16 1.2 v current sense input bias current isi current sunk by pin 16 (npn base ) 1 m a maxmum external power transistor on time tonmax % of h-period @ f0=27khz (16) 100 % b+ output low level saturation voltage b+osv v 28 with i 28 =10ma 0.25 v internal reference voltage iv ref on error amp (+) input for subaddress 0b byte 1000000 4.8 v table 10. vertical section electrical characteristics (continued) parameter symbol conditions min typ max unit deflection processor for multisync monitors s1d2511b01 15 internal reference voltage adjustment range v refadj byte 111111 byte 000000 +20 -20 % % threshold for step-up/step-down selec- tion dwmsel pin 16 6 v falling time t fb+ pin 28 100 ns table 12. b+ section electrical characteristics s1d2511b01 deflection processor for multisync monitors 16 notes; 1. duty cycle is the ratio of power transistor off time period. power transistor is off when output transistor is off. 2. initial condition for safe operation start up. 3. s and c correction are inhibited so the output sawtooth has a linear shape. 4. with register 07 at byte x0xxxxxx (s-correction control is inhibited) then the s correction is inhibited, consequently the sawtooth has a linear shape. 5. with register 08 at byte x0xxxxxx (c-correction control is inhibited) then the c correction is inhibited, consequently the sawtooth has a linear shape. 6. it is frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on pin 22, and with a constant ramp amplitude. 7. these parameters are not tested on each unit. they are measured during out internal qualification. 8. refers to notes 4 & 5 from last section. 9. th is the horizontal period. 10. these parameters are not tested on each unit. they are measured during our internal qualification procedure which incudes characterization on batches comming from corners of our processes and also temperature char acterization. 11. see figure 11 for explanation of reference phase. 12. see figure 15. 13. this is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on pin 22 and with a constant ramp amplitude. 14. tv is the vertical period. 15. when not used the dc breathing control pin must be connected to 12v. 16. the external power transistor is off during 400ns of the hfocuscap discharge. deflection processor for multisync monitors s1d2511b01 17 figure 1. vertical dynamic focus function figure 2. e/w output figure 3. dynamic horizontal phase control output vdf dc vdf amp a b ew para a b ew dc ew para a b spb para dhpc pc s1d2511b01 deflection processor for multisync monitors 18 figure 4. typical vertical output waveforms function sub address pin byte specification picture image vertical size 05 23 10000000 11111111 vertical position dc control 06 23 x0000000 x1000000 x1111111 3.2v 3.5v 3.8v vertical s linearity 07 23 x0xxxxxx inhibited x1111111 vertical c linearity 08 23 x1000000 x1111111 v outdc v outdc 2.25v 3.75v vpp d v vpp d v =4% vpp vpp d v d v =3% vpp d v d v =3% vpp deflection processor for multisync monitors s1d2511b01 19 figure 5. geometry output waveforms function sub address pin byte specification picture image key stone (trapezoid) control 09 24 ewamp typ. 10000000 1111111 e/w (pin cushion) control 0a 24 keystone inhibited 1x000000 1x111111 parallelogram control 0e internal spb inhibited x1000000 x111111 side pin balance control 0d internal parallelogram inhibited x0000000 x1111111 vertical dynamic focus with horizontal 32 1.0v 1.0v 2.5v 2.5v 2.5v 0v 2.5v 3.7v 1.4% th 3.7v 1.4% th 1.4% th 3.7v 3.7v 1.4% th 2v s1d2511b01 deflection processor for multisync monitors 20 i 2 c bus address table slave address (8c): write mode sub address definition slave address (8d): read mode no sub address needed d8 d7 d6 d5 d4 d3 d2 d1 0 0 0 0 0 0 0 0 0 horizontal drive selection/horizontal duty cycle 1 0 0 0 0 0 0 0 1 horizontal position 2 0 0 0 0 0 0 1 0 forced frequcny /free running frequency 3 0 0 0 0 0 0 1 1 synchro priority / horizontal focus amplitude 4 0 0 0 0 0 1 0 0 refresh /horizontal focus keystone 5 0 0 0 0 0 1 0 1 vertical ramp amplitude 6 0 0 0 0 0 1 1 0 vertical position adjustment 7 0 0 0 0 0 1 1 1 s correction 8 0 0 0 0 1 0 0 0 c correction 9 0 0 0 0 1 0 0 1 e/w keystone a 0 0 0 0 1 0 1 0 e/w amplitude b 0 0 0 0 1 0 1 1 b+ reference adjustment c 0 0 0 0 1 1 0 0 vertical moire d 0 0 0 0 1 1 0 1 side pin balance e 0 0 0 0 1 1 1 0 parallelogram f 0 0 0 0 1 1 1 1 vertical dynamic focus amplitude deflection processor for multisync monitors s1d2511b01 21 i 2 c bus address table ( continued ) d8 d7 d6 d5 d4 d3 d2 d1 write mode 00 hdrive 0, off [1],on horizontal duty cycle [0] [0] [0] [0] [0] 01 xray 1,reset [0] horizontal phase adjustment [1] [0] [0] [0] [0] [0] [0] 02 forced frequency free running frequency 1,on, [0],off 1,f0x2 [0],f0x3 [0] [0] [0] [0] [0] 03 sync 0, comp [1], sep horizontal focus amplitude [1] [0] [0] [0] [0] 04 detect refresh [0], off horizontal focus keystone [1] [0] [0] [0] [0] 05 vramp 0, off [1], on vertical ramp amplitude adjustment [1] [0] [0] [0] [0] [0] [0] 06 vertical position adjustment [1] [0] [0] [0] [0] [0] [0] 07 s select 1, on [0] s correction [1] [0] [0] [0] [0] [0] 08 c select 1, on [0] c correction [1] [0] [0] [0] [0] [0] 09 ew key 0, off [1] east/west keystone [1] [0] [0] [0] [0] [0] 0a ew sel 0, off [1] east/west amplitude [1] [0] [0] [0] [0] [0] [0] 0b test h 1, on [0], off b+ reference adjustment [1] [0] [0] [0] [0] [0] [0] 0c test v 1, on [0], off moire 1, on [0] vertical moire [0] [0] [0] [0] [0] 0d spb sel 0, off [1] side pin balance [1] [0] [0] [0] [0] [0] 0e parallelo 0, off [1] parallelogrm [1] [0] [0] [0] [0] [0] 0f vertical dynamic focus amplitude [1] [0] [0] [0] [0] [0] s1d2511b01 deflection processor for multisync monitors 22 [ ] initlal value operating description general considerations power supply the typical values of the power supply voltages vcc and v dd are respectively 12v and 5v. perfect operation is obtained if vcc and v dd are maintened in the limits: 10.8 to 13.2v and 4.5 to 5.5v. in order to avoid erratic operation of the circuit during transient phase of vcc switching on, or switching off, the value of vcc is monitored and the outputs of the circuit are inhibited if vcc is less than 7.5v typically. in the same manner, v dd is monitored and internal set-up is made until v dd reaches 4v (see i 2 c control table for power on reset). in order to have a very good power supply rejection, the circuit is internally powered by several internal voltage references (the unigue typical value of which is 8v). two of these voltage references are externally accessible, one for the vertical part and on one for the horizontal one. if needed, these voltage references can be used (until iload is less than 5ma). furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor connected to ground, in order to minimize the noise and consequently the ? jitter ? on vertical and horizontal output signals. i 2 c control kb2511 belongs to the i 2 c controlled device family, instead of being controlled by dc voltage on dedicated control pins, each adjustment can be realized through the i 2 c interface. the i 2 c bus is a serial bus with a clock and a data input. the general function and the bus protocol are specified in the philips-bus data sheets. the interface (data and clock) is ttl-level compatible. the internal threshold level of the input comparator is 2.2v (when v dd is 5v). spikes of up to 500ns are filtered by an integrator and maximum clock speed is limited to 400khz. the data line (sda) can be used in a bidirectional way that means in read-mode the ic clocks out a reply informa- tion (1byte) to the micro-processor. the bus protocol prescribes always a full-byte transmission. the first byte after the start condition is used to trans- mit the ic-address (hexa 8c for write, 8d for read). write mode in write mode the second byte sent contains the subaddress of the selected function to adjust (or controls to affect) and the third byte the corresponding data byte. it is possible to send more than one data byte to the ic. if after the third byte no stop or start condition is detected, the circuit increments automatically the momentary subaddress in the subaddress counter by one (auto-increment mode). so it is possible to transmit immediately the next data bytes without sending the ic address or subaddress. it can be useful so as to reinitialize the whole controls very quickly (flash manner). this procedure can be finished by a stop condition. the circuit has 16 adjustment capabilities: 3 for horizontal part, 4 for vertical one, 2 for e/w correction, 2 for the dynamic horizontal phase control, 1 for moire option, 3 for horizontal and vertical dynamic focus and 1 for b+ reference adjustment. 17 bits are also dedicated to several controls (on/off, horizontal forced frequency, sync priority, detection refresh and xray reset). read mode 00 hlock 0, on [1], no vlock 0, on [1], no xray 1,on [0],off polarity detection synchro detection h/v pol [1],negative v pol [1], negative vext det [0],no det h/v det [0],no det v det [0], nodet deflection processor for multisync monitors s1d2511b01 23 read mode during read mode the second byte transmits the reply information. the reply byte contains horizontal and vertical lock/unlock status, xray activated or not, the horizontal and vertical polarity detection. it also contains synchro detection status that is useful for m p to assign sync priority. a stop condition always stops all activities of the bus decoder and switches the data and the clock line (sda and scl) to high impedance. see i 2 c subaddress and control tables. sync processor the internal sync processor allows the s1d2511b01 to accept any kind of input synchro signals: - separated horizontal & vertical ttl-compatible sync signals, - composite horizontal & vertical ttl-compatible sync signals. sync identification status the mcu can read (address read mode : 8d) the status register via the i 2 c bus, and then select the sync priority depending on this status. among other data this register indicates the presence of sync pulses on h/hvin, vsyncin and(when 12v is sup- plied) whether a vext has been extracted from h/hvin. both horizontal and vertical sync are detected even if only 5v is supplied. in order to choose the right sync priority the mcu may proceed as follows(see i 2 c address table): - refresh the status register, - wait at least for 20ms(max. vertical period), - read this status register, sync priotity choice should be: of course, when choice is made, one can refresh the sync detections and verify that extracted vsync is present and that no sync change occured. sync processor is also giving sync polarity information. ic status the ic can inform the mcu about the 1st horizontal pll and vertical section status, and about the xary protection (activated or not). resetting the xray internal latch can be done either by decreasing the vcc supply or directly resetting it via the i 2 c interface. sync inputs both h/hvin and vsyncin inputs are ttl compatible trigger with hysterisis to avoid erratic detection. both inputs include a pull up register connected to v dd . sync processor output the sync processr indicates on the hlockout pin whether 1st pll is locked to an incoming horizontal sync. hlockout is a ttl compatible cmos output. its level goes to high when locked. in the same time the d8 bit of the status regiser is set to 0. this information is mainly used to trigger safety procedures(like reducing b+ value) as soon as a change is detected on the incoming sync. further to this, it may be used in an automatic procedure for vext det h/v det v det sync priority subaddress 03 (d8) comment sync type no yes yes 1 separated h & v yes yes no 0 composite ttl h & v s1d2511b01 deflection processor for multisync monitors 24 free running frequency(fo) adjustment. sending the desired fo on the sync input and progressively decreasing the free running frequently i 2 c register value(address 02), the hlockout pin will go high as soon as the proper setting is reached. setting the free run- ning frequency this way allows to fully exploit the s1d2511b01 horizontal frequency range. horizontal part internal input conditions horizontal part is internally fed by synchro processor with a digital signal corresponding to horizontal synchro pulses or to ttl composite input. concerning the duty cycle of the input signal, the following signals (positive or negative)may be applied to the circuit. using internal integration, both signals are recognized on condition that z/t < 25%, synchronisation occurs on the leading edge of the internal sync signal. the minimum value of z is 0.7 m s. figure 6. an other integration is able to extract vertical pulse of composite synchro if duty cycle is more than 25% (typically d = 35%) (7) figure 7. the last feature performed is the equalizing pulses removing to avoid parasitic pulse on phase comparator input which is intolerent to wrong or missing pulse. pll1 the pll1 is composed of a phase comparator, an external filter and a voltage control oscillator (vco). the phase comparator is a phase frequency type designed in cmos technology. this kind of phase detector avoids locking on false frequencies. it is followed by a charge pump, composed of two current sources sunk and sourced (i = 1ma typ. when locked, i = 140ma when unlocked). this difference between lock/unlock permits a smooth catching of horizontal frequency by pll1. this effect is reinforced by an internal original slow down system when pll1 is locked avoiding horizontal too fast frequency change. the dynamic bahaviour of the pll is fixed by an external filter which integrates the current of the charge pump. a crc filter is generally used (see figure 8 ) z t z d d c tramext deflection processor for multisync monitors s1d2511b01 25 figure 8. pll1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong pulse on phase comparator. the inhibition results from the opening of a switch located between the charge pump and the filter (see figure 9 ). the vco uses an external rc network. it delivers a linear sawtooth obtained by charge and discharge of the capacitor, by a current proportionnal to the current in the resistor. typical thresholds of sawtooth are 1.6v and 6.4v. figure 9. block diagram 7 pll1f 1.8k w 4.7uf 1uf input interface comp1 charge pump pll inhibition vco 7 8 9 lockdet 8 phase adjust osc i 2 c hpos adj. low high e2 tramext hsync h-lockcap lock/unlock status tramext i 2 c smfe mode pll1f r0 c0 s1d2511b01 deflection processor for multisync monitors 26 figure 10. details of vco the control voltage of the vco is typically comprised between 1.33v and 6v (see figure 10). the theorical frequency range of this vco is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to clamp intervention on filter lowest value. to avoid spread of external components and the circuit itself, it is possible to adjust free running frequency through i 2 c. this adjustment can be made automatically on the manufacturing line without manual operation by using hlock/unlodk information. the adjustment range is 0.8 to 1.3 f0 (where 1.3 f0 is the free running frequency at power on reset). the sync frequency has to be always higher than the free running frequency. as an example for a synchro range from 24khz to 100khz, the suggested free running frequency is 23khz. an other feature is the capability for mcu to force horizontal frequency throw i 2 c to 2xf0 or 3xf0 (for burn in mode or safety requirement). in this case, inhibition switch is opened leaving pll1 free but voltage on pll1 filter is forced to 2.66v for 2xf0 or 4.0v for 3xf0. the pll1 ensures the coincidence between the leading edge of the synchro signal and a phase reference obtained by comparism between the sawtooth of the vco and an internal dc voltage i 2 c adjustable between 2.65v and 3.75v (corresponding to 10%) (see figure 11) figure 11. pll1 timing diagram 7 6 a 2 4 i 0 2 i d + - + - 6.4v + - rs flip flop 5 loop filter (0.80 s1d2511b01 deflection processor for multisync monitors 28 output section the h-drive signal is transmitted to the output through a shaping block ensuring ts and i 2 c adjustable duty cycle. in order to secure scanning power part operation, the output is inhibited in the following circumstances: - vcc too low - xray protection activated - during horizontal flyback - h drive i 2 c bit control is off. the output stage is composed of a npn bipolar transistor. only the collector is accessible (see figure 14). figure 14. the output npn is in off-state when the power scanning transistor is also in off-state. the maximum output current is 30ma, and the corresponding voltage drop of the output v cesat is 0.4v typically. it is evident that the power scanning transistor cannot be directly driven by the integrated circuit. an interface has to be designed between the circuit and the power transistor which can be of bipolar or mos type. x-ray protection the activation of the x-ray protection is obtained by application of a high level on the x-ray input (8v on pin 25). it inhibits the h-drive and b+ outputs. this protection is latched; it may be reset either by vcc switch off or by i 2 c(see figure 15). horizontal and vertical dynamic focus the s1d2511b01 delivers and horizontal parabola added on a vertical parabola wavefrom on pin 10. this horizon- tal parabola is performed from a sawtooth in phase with flyback pulse middle. this sawtooth is present on pin 9 where the horizontal focus capacitor is the same as c0 to obtain a controlled amplitude (from 2 to 4.7v typically). symmetry (keystone) and amplitude are i 2 c adjustable (see figure 16). vertical dynamic focus is tracked with vpos and vamp. its amplitude can be adjusted. it is also affected by s and c corrections. this positive signal has to be connected to the crt focusing grids. 26 h-drive deflection processor for multisync monitors s1d2511b01 29 figure 15. safety functions block diagram figure 16. - + - + s r q i 2 c drive on/off vcc checking vcc vscinh xray protection xray vcc off or i 2 c reset horizontal flyback 0.7v i 2 c ramp on/off horizontal output inhibition vertical output inhibition bout 400ns 4.7v 2v 2v moire output horizontal flyback horizontal flyback internal triggerd cap sawtooth horizontal focus horizontal dynamic focus parabola output s1d2511b01 deflection processor for multisync monitors 30 vertical part geometric corrections the principle is represented in figure 17. figure 17. geometric correcitions principle starting from the vertical ramp, a parabola shaped current is generated for e/w correction, dynamic horizontal phase control correction, and vertical dynamic focus correction. the base of the parabola generator is an analog multiplier, the output current of which is equal to: d i = k ( v out - v dcmid ) 2 where vout is the vertical output ramp(typically between 2 and 5v) and v dcmid is 3.5v(for v ref-v =8v). the vout sawtooth is typically centered on 3.5v. by changing the vertical position, the sawtooth shifts by 0.3v. in order to keep a good screen geometry for any end user preference adjustment we implemented the geometry tracking. due to large output stages voltage range (e/w, focus), the combination of tracking function with maximum verti- cal amplitude max or min vertical position and maximum gain on the dac control may lead to the output stages saturation. this must be avoided by limiting the output voltage by appropriate i 2 c registers values. for e/w part and dynamic horizontal phase control part, a sawtooth shaped differential current in the following form is generated: d i ? = k ? ( v out - v dcmid ) 2 then d i and d i ? are added together and converted into voltage for the e/w part. each of the two e/w components or the two dynamic horizontal phase control ones may be inhibited by their own i 2 c select bit. the e/w parabola is available on pin 24 by the way of an emitter follower which has to be biased by an external resistor (10k w ). it can be dc coupled with external circuitry. vertical dynamic focus is combined with horizontal one on output pin 10. dynamic horizontal phase control current drives internally the h-position, moving the hfly position on the horizontal sawtooth in the 1.4% th both on side pin balance and parallelogrm. vertical ramp v out v dcmid (3.5v) 2 + amp ew amp keystone sidepin amp + parallelogram to horizontal phase sidepin balance output current ew output dynamic focus i parabola generator v.focus 10 24 horizontal dynamic focus + v dcmid (3.5v) v dcmid (3.5v) 23 deflection processor for multisync monitors s1d2511b01 31 ew ewout = 2.5v + k1 ( v out - v dcmid ) 2 + k2 ( v out - v dcmid ) k1 is adjustable by ew amplitude i 2 c register k2 is adjustable by keystone i 2 c register dynamic horizontal phase control iout = k3 ( v out - v dcmid ) 2 + k4 ( v out - v dcmid ) k4 is adjustable by side pin balance i 2 c register k3 is adjustable by parallelogram i 2 c register. function when the synchronisation pulse is not present, an internal current source sets the free running frequency. for an external capacitor, c osc = 150nf, the typical free running frequency is 100hz. typical free running frequency can be calculated by: a negative or positive ttl level pulse applied on pin 2 (vsync) as well as a ttl composite sync on pin 1 can syn- chronise the ramp in the range [fmin, fmax]. this frequency range depends on the external capacitor connected on pin 22. a capacitor in the range [150nf, 220nf] 5% is recommanded for application in the following range: 50hz to 165hz. typical maximum and minimum frequency, at 25 c and without any correction (s correction or c correction), can be calculated by: f (max.) = 2.5 x f 0 and f (min.) = 0.33 x f 0 if s or c corrections are applied, these values are slighty affected. if a synchronisation pulse is applied, the internal oscillator is automaticaly caught but the amplitude is no more con- stant. an internal correction is activated to adjust it in less than a half a second : the highest voltage of the ramp pin 22 is sampled on the sampling capacitor connected on pin 20 at each clock pulse and a transconductance ampli- fier generates the charge current of the capacitor. the ramp amplitude becomes again constant. the read status register enables to have the vertical lock-unlock and the vertical sync polarity informations. it is recommanded to use a agc capacitor with low leakage current. a value lower than 100na is mandatory. good stability of the internal closed loop is reached by a 470nf 5% capacitor value on pin 20 (vagc) f 0 (hz)= 1.5 10 -5 c osc 1 s1d2511b01 deflection processor for multisync monitors 32 figure 18. agc loop block diagram i 2 c control adjustments then, s and c correction shapes can be added to this ramp. this frequency independent s and c corrections are generated internally. their amplitude are adjustable by their respective i 2 c register. they can also be inhibited by their select bit. endly, the amplitude of this s and c corrected ramp can be adjusted by the vertical ramp amplitude control register. the adjusted ramp is available on pin 23 (vout) to drive an external power stage. the gain of this stage is typically 25% depending on its register value. the mean value of this ramp is driven by its own i 2 c register (vertical position). its value is vpos = 7/16 v ref 300mv. usually vout is sent through a resistive divider to the inverting input of the booster. since vpos derives from v ref-v , the bias voltage sent to the non-inverting input of booster should also derive from v ref-v to optimize the accuracy(see application diagram). basic equations in first approximation, the amplitude of the ramp on pin 23 (vout) is: v out - vpos = ( v osc - v dcmid ) ( 1 + 0.25 (v amp ) ) with: - v dcmid = 7/16 v ref ( typically 3.5v, the middle value of the ramp on pin 22) - v osc = v22 ( ramp with fixed amplitude) - vamp = - 1 for minimum vertical amplitude register value and +1 for maximum - vpos is calculated by : vpos = v dcmid + 0.3vp with vp equals -1 for minimum vertical position register value and +1 for maximum the current available on pin 22 is : 2 synchro oscillator 20 - + 22 switch dlech 23 + - v-sync polarity disch. osc cap charge current transconductance amplifier ref samp cap sampling s correction vs_amp sub07/8bits cor-c sub08/6bits c correction vlow 18 vert_amp sub05/7bits vmoire sub0c/5bits vosition sub06/7bits vout breath i osc = v ref c osc f 8 3 deflection processor for multisync monitors s1d2511b01 33 with c osc : capacitor connected on pin 22 f: synchronisation frequency. vertical moire by using the vertical moire, vpos can be modulated from to frame. this function is intended to cancel the fringes which appear when line to line interval is very close to the crt vertical pitch. the amplitude pf the modulation is controlled by register vmoire on sub-off via the control bit d7. dc/dc converter part this unit controls the switch-mode dc/dc con-verter. it converts a dc constant voltage into the b+ voltage (roughly proportional to the horizontal frequency)necessary for the horizontal scanning. this dc/dc converter can be configured either in step-up or step-down mode. in both cases it oper-ates very similarly to the well known uc3842. step-up mode operating description - the powermosisswitched-onduringthe flyback (at the beginning of the positive slope of the horizontal focus sawtooth). - the power mos is switched-off when its current reachesa predeterminedvalue. forthispurpose, a sense resistor is inserted in its source. the voltage on this resistor is sent to pin16 (i sense ). - the feedback(coming either from the ehv or from the flyback) is divided to a voltage close to 4.8v and com- pared pared to the internal 4.8v reference(i vref ). the difference is amplified by an error amplifier, the output of which controls the power mos switch-off current. main features - switching synchronized on the horizontal fre-quency, - b+ voltage always higher than the dc source, - current limited on a pulse-by-pulse basis. step-down mode in step-down mode, the isense information is not used any more and therefore not sent to the pin16. this mode is selected by connecting this pin16 to a dc voltage higher than 6v (for example v ref-v ). operating description - the powermosis switched-onas for thestep-up mode. - the feedbackto the error amplifier is done as for the step-up mode. - the power mos is switched-off when the hfocuscap voltage get higher than the error amplifier output voltage main features - switching synchronized on the horizontal fre-quency, - b+ voltage always lower than the dc source, - no current limitation. s1d2511b01 deflection processor for multisync monitors 34 application circuit 1 2 16 15 14 13 12 11 10 9 3 4 5 6 7 8 mc14528 vcc=12v 50k 50k 5v 1k 6.8k 1k 12v hsync 1k vsync 22nf 100v 820pf 50v 1% p 1.8k + 4.7uf 50v 10nf 100v mp 0.1uf 22k + 100uf 1uf 820pf 10k afc + 4.7uf 0.1uf 1m 33k 3.3k 50k 22k 100 100 sda scl + 100uf 10k hout 22k 10k 10k afc 150nf 100v 1% p 470nf 63v p 0.1uf 0.1uf 10k + 47uf 50v 50k 1k 1k 5v 1 2 3 4 sclk scl sda 2 3 4 5 6 7 14 13 12 11 10 9 8 1 74hct125 sdat ack 100k 47pf hout 0.1uf + 100uf 33pf 10k afc 47pf 100k sda 31 vcc 29 b+out 28 gnd 27 xray 25 ewout 24 vout 23 vscap 22 h_out 26 vagccap 20 breath 18 v_ref 21 vgnd 19 comp 14 vsync_in 2 pll2c 4 co 5 ro 6 pll1f 7 hposition 8 hfocuscap 9 h_focus 10 hgnd 11 hfly 12 h_ref 13 regin 15 scl 30 hsync_in 1 5v 32 i_sense 16 b+gnd 17 h_lockout 3 kb2511b s1d2511b |
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